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Ph.D. in Information and Communications Technologies

Marco Angioli

Keeping up with the growing demands of AI requires intervention across the full design stack — from algorithm reformulation to silicon.

I build that bridge — designing dedicated silicon accelerators and brain-inspired algorithms that bring AI to the edge. My work spans Hyperdimensional Computing, RISC-V custom ISA extensions, and contextual bandit algorithms on embedded platforms, evaluated on FPGA and ASIC from algorithm to GDSII.

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Marco Angioli
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01 About Me

I am a Ph.D. candidate in Information and Communications Technologies at Sapienza University of Rome, specializing in the algorithmic-hardware co-design of dedicated accelerators for next-generation AI on resource-constrained devices.

My work spans the full design stack — from mathematical reformulation of learning algorithms and brain-inspired computing paradigms to RTL design, FPGA prototyping, and ASIC synthesis — with a relentless focus on minimizing energy consumption and execution time for edge intelligence.

I have published 22 papers (10 as first author) across top IEEE and ACM venues, and delivered 160 hours of university tutoring on FPGA design and hardware-accelerated AI for Master's students. My open-source framework AeneasHDC is the first automatic platform for deploying Hyperdimensional Computing models on FPGAs.

Affiliation

Sapienza University of Rome
DIET Department, Digital Systems Lab

Supervisor

Prof. Mauro Olivieri

Visiting Research

AASS Research Centre, Örebro University
Sweden — Mar 2025 – Jul 2025

Languages

Italian (Native), English (C1), French (A2)

02 Research

My research enables efficient embedded intelligence on resource-constrained devices through algorithmic-hardware co-design, spanning three core pillars:

Hyperdimensional Computing

Brain-inspired computing with high-dimensional distributed representations. I design dedicated hardware accelerators for HDC/VSA models, achieving up to three orders of magnitude speedup vs. software implementations.

HDC/VSAMCRBinary Spatter CodesFPGAASIC

Hardware Acceleration for AI

Custom ISA extensions, reconfigurable coprocessors, and optimized arithmetic units targeting AI workloads on embedded platforms. Built on the open-source RISC-V Klessydra core family, my accelerators deliver orders-of-magnitude speedup on learning tasks with full GCC compiler integration, evaluated on both FPGA and ASIC (GF22FDX).

RISC-VCustom ISAVector ProcessingKlessydraFPGAASIC

Embedded Online Learning

Reformulating learning paradigms by exploiting neuro-inspired representations for sequential decision-making on resource-constrained devices. My HD-CB framework maps contextual bandit problems into high-dimensional spaces, achieving competitive performance with orders-of-magnitude lower complexity than traditional approaches.

Contextual BanditsLinUCBHD-CBEdge AI
103x Up to three orders of magnitude speedup on HDC tasks (HDCU & MCR accelerators)
>90% Energy reduction for contextual bandits on embedded systems
93.99% Energy savings with novel variable-latency divider (FPGA & ASIC)

03 Publications

22 publications including 8 journal articles and 14 conference papers. 10 as first author.

2025
Journal

Efficient Hyperdimensional Computing with Modular Composite Representations

M. Angioli, C. J. Kymn, A. Rosato, A. Loutfi, M. Olivieri, D. Kleyko

IEEE Emerging Topics in Computational Society (submitted)

2025
Journal

Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems

M. Angioli, M. Barbirotta, A. Cheikh, A. Mastrandrea, F. Menichelli, M. Olivieri

ACM Trans. Embedded Comput. Syst., 2025. DOI: 10.1145/3736226

2025
Journal

HD-CB: The First Exploration of Hyperdimensional Computing for Contextual Bandits Problems

M. Angioli, A. Rosato, M. Barbirotta, R. Martino, F. Menichelli, M. Olivieri

IEEE Open J. Comput. Soc. (submitted)

2025
Journal

Configurable Hardware Acceleration for Hyperdimensional Computing Extension on RISC-V

R. Martino, M. Angioli, A. Rosato, M. Barbirotta, A. Cheikh, M. Olivieri

IEEE Trans. Comput. (submitted)

2025
Journal

Fault Tolerant Voting Circuits: A Dual-Modular-Redundancy Approach for SET Mitigation

M. Barbirotta, M. Angioli, A. Mastrandrea, F. Menichelli, M. Pisani, M. Olivieri

Microproc. Microsyst., 2025

2024
Journal

Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme

M. Angioli, M. Barbirotta, A. Cheikh, A. Mastrandrea, F. Menichelli, S. Jamili, M. Olivieri

IEEE Trans. Comput., vol. 73, no. 7, pp. 1767–1779, 2024

2024
Journal

Dynamic Triple Modular Redundancy in Interleaved Hardware Threads

M. Barbirotta, F. Menichelli, A. Cheikh, A. Mastrandrea, M. Angioli, M. Olivieri

IEEE Access, vol. 12, pp. 95720–95735, 2024

2023
Journal

Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

M. Barbirotta, A. Cheikh, A. Mastrandrea, F. Menichelli, M. Angioli, S. Jamili, M. Olivieri

Electronics, vol. 12, no. 17, 2023

2025
Conference

HD-CB_BIN: A Lightweight Approach for Contextual Bandit Learning in Real-Time Applications

M. Angioli et al.

IEEE IJCNN, Rome, 2025 (Accepted)

2025
Conference

A Novel ML Framework for Drowsiness Detection Using an Electrostatic Wearable Sensor and HDC

L. Ferri, M. Gazzanti P. di Cotrone, M. Angioli et al.

IEEE MetroInd4.0&IoT, 2025

2024
Conference

AeneasHDC: An Automatic Framework for Deploying HDC Models on FPGAs

M. Angioli, S. Jamili, M. Barbirotta et al.

IEEE IJCNN, Yokohama, 2024

2024
Conference

Exploring Variable Latency Dividers in Vector Hardware Accelerators

M. Angioli, M. Barbirotta, A. Cheikh, A. Mastrandrea, M. Olivieri

IEEE PRIME, Larnaca, 2024

2024
Conference

SE-UVM: An Integrated Simulation Environment for Single Event Induced Failures Characterization

M. Barbirotta, M. Angioli et al.

IEEE DFT, Oxfordshire, 2024

2024
Conference

DMR Voting Circuits for Single-Event-Transient Mitigation

M. Barbirotta, M. Angioli et al.

IEEE DFT, Oxfordshire, 2024

2024
Conference

Alternative Implementations of ECC in Register Files of a RISC-V Safety Critical Processor

M. Barbirotta, M. Angioli et al.

ApplePies, 2024

2023
Conference

Automatic HW Accelerators Reconfiguration through LinearUCB on a RISC-V Processor

M. Angioli, M. Barbirotta, A. Mastrandrea, S. Jamili, M. Olivieri

IEEE PRIME, Valencia, 2023

2023
Conference

Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Design

M. Barbirotta, M. Angioli et al.

ApplePies, 2023

2023
Conference

Homogeneous Tightly-Coupled Dual Core Lock-Step

M. Barbirotta et al. (incl. M. Angioli)

SIE, 2023

2023
Conference

Heterogeneous Tightly-Coupled Dual Core Architecture Against SEEs

M. Barbirotta et al. (incl. M. Angioli)

ApplePies, 2023

2023
Conference

A Universal HW Emulator for Verification IPs on FPGA

S. Jamili et al. (incl. M. Angioli)

ApplePies, 2023

2022
Conference

Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators

M. Angioli, M. Barbirotta, A. Cheikh et al.

ApplePies, Genova, 2022

2022
Conference

Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor

S. Jamili et al. (incl. M. Angioli)

ApplePies, 2022

04 Open Source & Projects

Featured Open Source

AeneasHDC

The first open-source automatic framework for generating flexible HDC hardware accelerators on FPGAs. Supports classification, regression, and clustering with 22 configurable parameters. Automates the full pipeline: model configuration, software instantiation (Python, MATLAB, C++), HLS-based HW generation, Vivado synthesis, and automated characterization reports.

PythonMATLABC++HLSVivadoFPGA
View on GitHub
Configure
Generate
Synthesize
Report

HDCU

klessydra / HDCU

Open-source reconfigurable hyperdimensional computing coprocessor integrated into the Klessydra-T03 RISC-V core. Features configurable SIMD parallelism, runtime hypervector size configuration, and custom C intrinsics for ML workloads.

VHDL C RISC-V Custom ISA
View on GitHub

HDCU Stand-Alone

RoMartino / HDCU-Stand-Alone

Stand-alone version of the HDCU accelerator, decoupled from the Klessydra processor ecosystem for flexible integration and design-space exploration of the HDC hardware unit in isolation.

VHDL HDC FPGA HW Accelerator
View on GitHub

Technical Expertise

Hardware Design

VHDLSystemVerilogVivadoVivado HLSSynopsys Fusion CompilerModelSimUVM

Programming

CC++PythonBashMATLABTcl

AI / ML

PyTorchTensorFlowscikit-learnNumPyPandas

Embedded Systems

RISC-VARM Cortex-MSTM32PetalinuxYoctoAXISPI/I2C

05 Experience & Education

Experience

Jan 2026 – Jun 2026

Research Collaborator

Sapienza University of Rome

Post-doctoral collaboration on HDC algorithm analysis and dedicated hardware solutions for FPGA and ASIC implementation.

Mar 2025 – Jul 2025

Visiting Researcher

AASS Research Centre, Örebro University, Sweden

Designed the first MCR hardware accelerator. Joint manuscript with Dr. Denis Kleyko. Evaluated across 123 classification datasets.

Nov 2022 – Dec 2025

Doctoral Researcher

Digital Systems Lab, DIET Dept., Sapienza

Three-year program on algorithmic-hardware co-design: HDC accelerators, RISC-V extensions, variable-latency arithmetic, contextual bandits.

Jan 2022 – Dec 2024

University Tutor — 160 hours

Sapienza University of Rome

Digital System Programming (140h) and Digital System Architectures (20h). Tutored 20+ Master's students on FPGA design and HW acceleration.

Education

Nov 2022 – May 2026

Ph.D. in ICT — Electronic Engineering

Sapienza University of Rome

Thesis: “Algorithmic Hardware Co-Design for Efficient Embedded Intelligence.” Evaluated on FPGA (Xilinx) and ASIC (GF22FDX) with RISC-V Klessydra cores.

Sep 2019 – Jul 2022

M.Sc. in Electronic Engineering

Sapienza University of Rome — 110/110 cum laude

Thesis on contextual bandit algorithms on RISC-V with reconfigurable vector acceleration. Up to 45x speedup on matrix operations.

Sep 2016 – Dec 2019

B.Sc. in Electronic Engineering

Sapienza University of Rome

Thesis: “State of the Art in Neuromorphic Computing.” Survey of spiking neural networks and brain-inspired architectures.

Selected Training

EFCL Winter School on Open Source IC Design — ETH Zurich, 2026
Synopsys Fusion Compiler (ASIC Flow) — Europractice, 2024
ACM/HiPEAC Summer School on HPC for AI — Barcelona, 2023
SystemVerilog & UVM — Europractice, 2023

06 Get in Touch

I am open to collaborations, visiting positions, and discussions about hardware-accelerated AI, HDC/VSA, or embedded intelligence. Feel free to reach out.

Email

marco.angioli@uniroma1.it

Academic Profile

Sapienza University of Rome

Location

Rome, Italy